The present invention relates to a fine variable delay circuit which is suitable for use as each of variable delay stages which are cascade-connected to form a variable delay circuit which is able to delay, for example, an input signal thereto for a desired period of time.
Generally speaking, CMOS logic circuits individually have inherent input-output delay times of their own depending on various conditions during manufacture. As compared with logic circuits formed by bipolar transistors, the CMOS circuits suffer their larger scattering delay time, and therefore, the use of such CMOS logic circuits for forming various circuits will lead to lack of a timing margin. A fine variable delay circuit is needed to correct variations in the input-output delay time of such a CMOS logic circuit.
FIG. 1A shows a conventional variable delay circuit formed by a plurality of cascade-connected variable delay stages to which the present invention is applicable. Variable delay stages 11, 12 and 13 are connected in series and the delay time of each stage is selectively variable by selecting one of two paths branched from its input under control of a multiplexer 14. In this example, the variable delay stage 11 has buffers 15 and 16 respectively provided in two paths, the variable delay stage 12 has one buffer 16 provided in only one of the two paths and the variable delay stage 13 has two series-connected buffers 16 provided in only one of the two paths. The propagation delay time Tpd of the buffer 16 is set to a value twice larger than the propagation delay time Tpd of the buffer 15. For instance, the buffer 15 may be formed by a series connection of two inverters, whereas the buffer 16 by a series connection of four inverters. By selective control of select signals SEL.sub.1, SEL.sub.2 and SEL.sub.3 for the multiplexers 14 of the respective variable delay stages 11, 12 and 13, the path between an input terminal 17 and an output terminal 18 is changed for each stage, whereby delay times 1, 2, . . . , 8 times as long as the propagation delay time Tpd of the buffer 15, respectively, are provided in this example.
In the case where a delay element 19 is provided in only one of the two paths in each of the variable delay stages 11, 12 and 13 as shown in FIG. 1B, the delays d.sub.1, d.sub.2 and d.sub.3 of the delay elements 19 are A, 2A and 4A, respectively, where A is a minimum resolution desired to obtain. In the case of n variable delay stages being connected, the delay d.sub.n of the delay element 19 in the nth stage is A2.sup.n-1.
With the prior art example depicted in FIG. 1A, it is difficult to raise or improve the resolution (i.e. to reduce the minimum variable step) partly because the delays of the buffers 15 and 16 are relatively large, for example, 200 to 500 pS and partly because the total propagation delay between the input and output terminals 17 and 18 consists in great part of a fixed delay. In other words, since the scattering of the delays of the buffers has an appreciable influence on the total propagation delay as a whole, it is difficult to raise the delay resolution within compensated scattering delay. In the case where the buffers 15 and 16 are fabricated as integrated circuits using CMOS's, the scattering of their delays is particularly large, making it more difficult to increase the resolution than in the case where bipolar transistors are used to form the buffers 15 and 16.
The circuit arrangement shown in FIG. 1B also utilizes the propagation delay of each delay element 19, which scatters due to varying conditions during manufacture, variations in the power supply voltage and ambient temperature and the scatter of the line capacity as well. Letting the delay resolution, i.e. the minimum variable step be represented by A, it is possible, ideally, that the nth variable delay stage selects the delay 0 or A2.sup.n-1 and that the delays ranging from 0 to A2.sup.n-1 are selectively set every step A at will by the variable delay circuit formed by a total of M variable delay stages. Accordingly, the following equation holds: EQU A2.sup.n-1 =A(2.sup.0 +2.sup.1 + . . . +2.sup.n-2)+A2.sup.0.
In practice, however, the delays of the respective delay stages scatter. Now, let the scattering or dispersion ratio of delay in each delay element be represented by .alpha.. In the worst case, there are the possibilities that the sum of delays in variable delay stages preceding a certain stage becomes minimum due to scattering and that the delay in that certain stage becomes maximum due to scattering, and even in such a case, the required delay resolution A must be secured. In the actual design of the variable delay circuit it is necessary, therefore, to predetermine the delays d.sub.1, d.sub.2, . . . of respective delay stages in anticipation of their scattering. That is, the delay d.sub.1, which satisfies (1+.alpha.)d.sub.1 =A, is determined for the first delay stage 11; the delay d.sub.2, which satisfies (1+.alpha.)d.sub.2 =d.sub.1 (1-.alpha.)+A, and hence is equal to 2A/(1+.alpha.).sup.2, is determined for the second delay stage 12; and the delay d.sub.3, which satisfies (1+.alpha. )d.sub.3 =(d.sub.1 +d.sub.2)(1-.alpha.), and hence is equal to 2A/(1+.alpha.).sup.3, is determined for the third delay stage 13. In the case where n delay stages are connected in cascade, the delay of the nth stage is D.sub.n =2.sup.n-.A/(1+.alpha.).sup.n, taking the scatter of the delay into account.
Thus the influence of the delay scattering or dispersion ratio .alpha. increases as the last delay stage is approached and the delay becomes smaller than that d.sub.n =2.sup.n-1.A in the ideal case, making it impossible to enlarge the range over which the delay of each delay stage is variable. In the case of using a CMOS gate array to form the delay element, the ratio .alpha. is usually around 0.6, and since this is an appreciably large value, the circuit which provides the desired delay would become inevitably large-scale, and hence is impractical.